AI-Fabrics is an innovative U.S. start-up building breakthrough technology for a new breed of networks that are purpose built for AI infrastructure buildout at scale.
To bring this vision to life, we’re expanding our US based R&D workforce and growing a second world-class team in Israel – with our new office located in Caesarea, just a short walk from the rail station.
This is a unique opportunity to help shape the future of AI hardware — and to build something meaningful from the ground up.
Senior RTL Designer
RTL Designer
Senior Verification Designer
Verification Designer
Senior RTL Integration Engineer
Location: Caesarea ,Israel
Senior RTL Designer
Responsibilities:
- Own the design and development of complex RTL blocks and micro-architectures of Networking connectivity products for AI cloud systems and data centers
- Define and implement hardware architecture from concept to production
- Collaborate with cross-functional teams including architecture, verification, Emulation, physical design and software.
- Design of IPs and SOC in a highly innovated Switch and NIC products.
- Act as a key contributor in shaping the technological direction and culture of the new Israeli site.
Requirements:
- 12+ years of hands-on experience in RTL design and micro-architecture (SystemVerilog/Verilog).
- B.Sc. in Electrical Engineering, Computer Engineering, or a related field – required.
- M.Sc. or Ph.D. – an advantage
- Proven track record in designing high-performance, scalable digital systems.
- Background in Networking architectures and IPs (Switches, NICs and smart-NICs)
- Relevant knowledge in Networking functions like packet processing, RDMA, Ethernet Serdes, PCIe switching, MAC design etc…
- Experience with RTL quality sign-off tools and methods (Lint, CDC, RDC, MCP etc….)
- Experience with ASIC/FPGA development flows and verification methodologies.
- Strong leadership skills and ability to drive complex projects independently.
- Excellent communication skills and fluency in English.
Apply to: [email protected]
RTL Designer
Responsibilities:
- Own the design and development of complex RTL blocks and micro-architectures for AI cloud systems and data centers.
- Define and implement hardware architecture from concept to production.
- Collaborate with cross-functional teams including architecture, verification, physical design and software.
- Design of IPs and SOC in a highly innovated Switch and NIC products.
- Act as a key contributor in shaping the technological direction of the new Israeli site.
Requirements:
- 5+ years of hands-on experience in RTL design and micro-architecture (SystemVerilog/Verilog).
- B.Sc. in Electrical Engineering, Computer Engineering, or a related field – required.
- M.Sc. or Ph.D. – an advantage
- Proven track record in designing high-performance, scalable digital systems.
- Background in Networking architectures and IPs (Switches, NICs and smart-NICs)
- Relevant knowledge in Networking functions like packet processing, RDMA, Ethernet Serdes, PCIe switching, MAC design etc…
- Experience with ASIC/FPGA development flows and verification methodologies.
- Strong leadership skills and ability to drive complex projects independently.
- Excellent communication skills and fluency in English.
- Job Title: Senior Design Verification Engineer
Apply to: [email protected]
Senior Verification Designer
Responsibilities:
- Build and own the verification strategy, planning, and execution for complex SoCs, IPs, and networking architectures (Switches, NICs…).
- Define and implement block-level and system-level verification environments from concept to production.
- Develop UVM/SystemVerilog testbenches, checkers, monitors, and coverage models to ensure functional correctness and performance.
- Drive coverage closure and signoff for high-performance networking architectures.
- Collaborate closely with architecture, RTL design, physical design, and software teams to identify corner cases and resolve issues.
- Act as a key contributor in shaping the verification methodology and infrastructure of the new Israeli site.
Requirements:
- 12+ years of hands-on experience in ASIC/FPGA verification using SystemVerilog, UVM, and advanced methodologies.
- B.Sc. in Electrical Engineering, Computer Engineering, Computer science or related field – required.
- M.Sc. or Ph.D. – an advantage.
- Proven track record in verifying high-performance, scalable digital systems.
- Strong background in networking architectures and IPs (Switches, NICs, SmartNICs).
- Relevant knowledge in networking functions such as packet processing, RDMA, Ethernet SerDes, PCIe switching, and MAC design.
- Experience with formal verification, emulation, and FPGA prototyping is a strong advantage.
- Strong leadership skills and ability to drive complex projects independently.
- Excellent communication skills and fluency in English.
Apply to: [email protected]
Verification Designer
Responsibilities:
- Lead the verification strategy, planning, and execution for complex SoCs, IPs, and networking architectures (Switches, NICs…).
- Define and implement block-level and system-level verification environments from concept to production.
- Develop UVM/SystemVerilog testbenches, checkers, monitors, and coverage models to ensure functional correctness and performance.
- Drive coverage closure and signoff for high-performance networking architectures.
- Collaborate closely with architecture, RTL design, physical design, and software teams to identify corner cases and resolve issues.
- Act as a key contributor in shaping the verification methodology and infrastructure of the new Israeli site.
Requirements:
- 5+ years of hands-on experience in ASIC/FPGA verification using SystemVerilog, UVM, and advanced methodologies.
- B.Sc. in Electrical Engineering, Computer Engineering, or related field – required.
- M.Sc. or Ph.D. – an advantage.
- Proven track record in verifying high-performance, scalable digital systems.
- Strong background in networking architectures and IPs (Switches, NICs, SmartNICs).
- Relevant knowledge in networking functions such as packet processing, RDMA, Ethernet SerDes, PCIe switching, and MAC design.
- Experience with formal verification, emulation, and FPGA prototyping is a strong advantage.
- Strong leadership skills and ability to drive complex projects independently.
- Excellent communication skills and fluency in English.
Apply to: [email protected]
Senior RTL Integration Engineer
Responsibilities:
- Lead the integration of complex RTL blocks and IPs into large-scale SoCs for AI cloud systems and data centers.
- Own and maintain the Front-end environment, integration TFM and data bases
- Define and implement chip- and subsystem-level integration architecture from concept to production.
- Perform RTL quality checks (Lint, CDC/RDC, power-aware verification, synthesis readiness).
- Drive integration flows for clock, reset, power domains, and interconnect fabrics.
- Collaborate with cross-functional teams including architecture, RTL design, verification, physical design, DFT, and software.
- Contribute to the design of highly innovative Switch and NIC products by ensuring seamless RTL integration.
- Act as a key contributor in shaping the integration methodologies and infrastructure of the new Israeli site.
Requirements:
- 12+ years of hands-on experience in RTL integration and front-end flows (SystemVerilog/Verilog).
- B.Sc. in Electrical Engineering, Computer Engineering, or a related field – required.
- M.Sc. or Ph.D. – an advantage.
- Proven track record in SoC integration and sign-off for high-performance, scalable digital systems.
- Background in networking architectures and IPs (Switches, NICs, SmartNICs).
- Relevant knowledge in networking functions such as packet processing, RDMA, Ethernet SerDes, PCIe switching, and MAC design.
- Solid experience with integration checks, synthesis flows, and low-power methodologies.
- Strong leadership skills and ability to drive complex integration projects independently.
- Excellent communication skills and fluency in English.
Apply to: [email protected]
