We are looking for a Formal Verification expert specializing in RTL/ASIC verification to work on a new cutting-edge application processor. The role involves ownership of formal methodologies, verification strategy definition, and close collaboration with architecture and design teams to ensure full functional correctness of complex processor units. Responsibilities: Understand high-level specifications and detailed requirements for application processor design logical units. Collaborate with cross functional teams such as architecture, design, and software teams on formal verification planning. Formal Verification expert to lead all formal activities for a new RISC-V application processor. Required Skills and Experience : BSc. in Electrical and/or Computer Engineering At least 6 years of experience with RTL ASIC verification, specializing in Formal verification. Knowledge and experience in one of the following: CPU, RISC-V architecture, micro-controllers, memory and cache controllers is an advantage. Experience with Verilog, System Verilog, SVA. Able to express complex concepts in fluent technical English. [email protected]

We are looking for a hands on Design Verification Team Lead to drive verification of next-generation wired/wireless peripheral subsystems that power Snapdragon platforms. As a DV Team Lead in the Peripheral group, you will own verification of complex IPs and subsystems, define and execute a UVM based verification strategy, and lead a small team of talented engineers to first time right silicon. This role requires proven leadership experience and strong technical expertise. This is a 5 days on site position in Haifa. What you’ll do: Define verification strategy, test plan, and coverage goals for complex peripheral IP and subsystem blocks Architect, develop, and maintain UVM& based constrained random verification environments Lead day to day activities of a small DV team: task planning, code and test plan reviews, mentoring, and technical guidance Drive debug of complex issues across RTL, testbench, and system level, working closely with design, emulation and validation teams Analyze and close functional and code coverage, drive quality metrics to tape out criteria Contribute to methodology and flow improvements across the Peripheral DV team Minimum qualifications: BSc/MSc in Electrical/Computer Engineering or related field At least 7 years of hands on verification experience using UVM and SystemVerilog Proven experience in leading and managing a team Strong background in digital design and SoC/IP architecture Proven technical leadership: Prior experience leading or mentoring engineers or Demonstrated ability and motivation to lead a small DV team (e.g., ownership of major IP, driving cross‑functional efforts) High technical proficiency in: UVM testbench architecture (agents, sequences, scoreboards, coverage) Constrained random, coverage driven verification Debugging complex failures in large scale regressions Scripting (Python/Perl/Tcl/shell) in a UNIX/Linux environment Preferred qualifications Experience with high speed peripherals (e.g., USB, PCIe, Display, SerDes, or similar I/O IP) Knowledge of low power, reset, and clock domain interactions at IP/SoC level Familiarity with regression management, metrics, and sign off criteria Experience working with global, cross site teams [email protected]

As an RTL Design Engineer, you would be responsible for one or more functional units of the micro-controller and application processor, while working closely with architecture, verification, modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals. An ideal candidate will have at least 8 years of work experience in microprocessor, SoC, memory controller and interconnect IP design. Responsibilities: Understanding the high-level specification and requirements of functional units of micro-controller and application processor products. Define the Micro-architecture for an unit and developing its RTL, including all design stages. Collaborate with verification team on the test plan development for the blocks and verification closure. Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets. Required Skills and Experience : Knowledge with CPU, micro-controllers, memory sub systems and bus architectures is a plus. BS in Electrical and/or Computer Engineering with up to 4 years of experience with RTL design. Experience with Verilog, coupled with design synthesis targeted to achieve specified frequency, power, and area targets. Processor system knowledge including basic understanding of SoC systems as well as operating system software. Great communication & teamwork skills. This position will be 5 days per week office based. [email protected]