Responsibilities:
Contribute to the architecture and microarchitecture definition of CPU features related to security, MMU, address translation, TLBs, page-table walks, virtualization, and memory protection.
Participate in the definition and review of security, isolation, and protection mechanisms in CPU and system-level interfaces.
Work with design and verification teams to translate architectural intent into hardware definitions, technical specifications and RTL implementation.
Collaborate with CPU design, verification, firmware/software, and system teams to develop and integrate new features while meeting functional, performance, power, and area goals.
Minimum Qualifications:
Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.
Experience with hardware design, microarchitecture, or architecture-related development flows.
Experience with architecture documentation, technical reviews, and requirement definition.
Familiarity with processor systems, memory subsystems, or bus/interconnect architectures.
Experience with RTL implementation and closure toward performance, power, and area goals.
Strong analytical, problem-solving, communication, and teamwork skills.
Experienced HW designers with relevant background are also encouraged to apply.
Preferred Background / Qualifications:
Experience with CPU, MMU, LSU, cache, interconnect, or related HW blocks architecture and microarchitecture.
Familiarity with security-related architecture topics such as isolation, privilege/security mechanisms, secure execution, memory safety, or related protection features.
Good understanding of one or more of the following: security-oriented memory protection, virtual memory/address translation, TLBs and page-table walks, virtualization and isolation, or CPU/SoC architecture.
Advantages:
Familiarity with broader security concepts such as confidential computing, trusted execution, threat modeling, security risk analysis, and platform security principles.
Understanding of security/performance/PPA tradeoffs, and awareness of mitigation-oriented design topics such as control-flow and side-channel related protections.
