## About the Role

A leading global semiconductor company is looking for talented and motivated Junior Engineers to join its Haifa-based team and contribute to next-generation SoC projects.

As part of the VLSI team within the Wired Connectivity group, you will work on cutting-edge high-speed interfaces and advanced connectivity solutions.

You will be involved in designing and verifying complex connectivity protocols, with a strong emphasis on low-power design and high performance. This is an excellent opportunity to work on advanced semiconductor technologies and contribute to innovative products shaping the future of connectivity.

## Key Responsibilities – Pre-Silicon Verification

– Develop and execute verification plans for complex connectivity IPs.
– Build, enhance, and maintain SystemVerilog/UVM verification environments.
– Create directed, constrained-random, stress, performance, power, and system-level test scenarios to validate architecture and real-world use cases.
– Develop assertions, functional coverage models, checkers, scoreboards, and signoff metrics to achieve verification closure.
– Debug RTL, testbench, and silicon bring-up issues using logs, waveforms, traces, and hardware debug data.
– Drive coverage closure, regression health, bug tracking, and verification signoff using functional, code, assertion, and scenario coverage metrics.