We are seeking highly experienced top talents and visionary hardware designers to contribute to the development of advanced AI connectivity architectures and shape.
Responsibilities:
• Lead the verification strategy, planning, and execution for complex SoCs, IPs, and networking architectures (Switches, NICs…).
• Define and implement block-level and system-level verification environments from concept to production.
• Develop UVM/SystemVerilog testbenches, checkers, monitors, and coverage models to ensure functional correctness and performance.
• Drive coverage closure and signoff for high-performance networking architectures.
• Collaborate closely with architecture, RTL design, physical design, and software teams to identify corner cases and resolve issues.
• Act as a key contributor in shaping the verification methodology and infrastructure of the new Israeli site.
Requirements:
• 5+ years of hands-on experience in ASIC/FPGA verification using SystemVerilog, UVM, and advanced methodologies.
• B.Sc. in Electrical Engineering, Computer Engineering, or related field – required.
• M.Sc. or Ph.D. – an advantage.
• Proven track record in verifying high-performance, scalable digital systems.
• Strong background in networking architectures and IPs (Switches, NICs, SmartNICs).
• Relevant knowledge in networking functions such as packet processing, RDMA, Ethernet SerDes, PCIe switching, and MAC design.
• Experience with formal verification, emulation, and FPGA prototyping is a strong advantage.
• Strong leadership skills and ability to drive complex projects independently.
• Excellent communication skills and fluency in English.
CV+5805@hrhome.co.il
